The XADIO 8 logic is programmed in a FPGA (VHDL) and therefore adaptible to customer needs,
i.e. different digital input/outputs allocation.
PCI Slot
PCI Busmaster DMA
Interrupt options: (32-bit register enabled interrupt generation)
- by each measurement in the register
- by reaching a timer value
- by change of a digital value
- by a filled buffer in main-memorz (copy out of the register)
- by zero-crossing of the encoder
Power Supply 5V, 2.5A |
